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checksyntax wyświetla bardzo dużo błędów w moim kodzie

anderson20
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Posty:26
Rejestracja:15 gru 2008, o 14:07
Lokalizacja:Poznań

Postautor: anderson20 » 3 lut 2009, o 22:14

a jak mam taką pętle:

Kod: Zaznacz cały

for i zmienna to 10 loop A_temp(i) := s; end loop;
to jak sobie z tym poradzić bo dałem tak, ale nie przechodzi post-synthesis:

Kod: Zaznacz cały

for i in 1 to 10 loop if(i>=zmienna)then A_temp(i) := s; end if; end loop;
takie coś się wyświetla:

Kod: Zaznacz cały

INFO:Xst:1433 - Contents of array <A> may be accessed with an index that exceeds the array size. This could cause simulation mismatch. INFO:Xst:1432 - Contents of array <A> may be accessed with a negative index, causing simulation mismatch. INFO:Xst:1433 - Contents of array <A> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
no a do tego pierwszego to o bounds mówi:
range bound must be a constant.

Piotr Czak
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Posty:22
Rejestracja:1 lut 2009, o 20:07
Lokalizacja:Wejherowo

Postautor: Piotr Czak » 4 lut 2009, o 08:07

Cześć

sprawa również bardzo prosta zamiast to dajemy downto obracamy zmienne dajemy exit i po sprawie, czyli dla przykładu:

Kod: Zaznacz cały

F1: for i 10 downto 0 loop A_temp(i) := s; exit F1 when (i < zmienna) end loop F1;
Podaj mi jeszcze jak masz zadeklarowany sygnał A_temp, s i zmienna, ponieważ te "INFO" mówi o czymś innym i tak na prawdę to nie jest ERROR tylko INFO wiec powinno działać.

Pozdrawiam

Edit: Code.
Ostatnio zmieniony 5 lut 2009, o 13:27 przez Piotr Czak, łącznie zmieniany 1 raz.

anderson20
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Posty:26
Rejestracja:15 gru 2008, o 14:07
Lokalizacja:Poznań

Postautor: anderson20 » 4 lut 2009, o 15:33

mam zadeklarowany taki typ:

Kod: Zaznacz cały

type tablica2 is array (1 to k_calk) of integer;
gdzie k_calk to przy deklaracji entity jest ustawione na 3;

Kod: Zaznacz cały

generic( k_calk: integer :=3 );
A_temp to zmienna typu tablica2, a A to sygnał typu tablica2. S to sygnał typu integer.
Całość wygląda tak:

Kod: Zaznacz cały

F0: for i in k_calk downto 1 loop A_temp(i) := s; exit F0 when (i<ind); end loop F0; A <= A_temp;
i to jest umieszczone w procesie odpowiednio w pewnych if-ach jeśli sa spełnione. Ale już nie pojawiaja się te błędy bo zmodyfikowałem trochę cały program.
Problem jaki mam to chodzi o to, że jak wciskam 2 razy na synthetize XST to czekam 5 minut i nic, czekam 10 i cały czas mieli a przy okazji wywala to info:

Kod: Zaznacz cały

========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "G:/Xilinx/generator_kombinacji/generator_komb.vhd" in Library work. Architecture behavioral of Entity generator_komb is up to date. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity <generator_komb> in library <work> (architecture <behavioral>) with generics. k_calk = 3 n_calk = 6 Building hierarchy successfully finished. ========================================================================= * HDL Analysis * ========================================================================= Analyzing generic Entity <generator_komb> in library <work> (Architecture <behavioral>). n_calk = 6 k_calk = 3 WARNING:Xst:819 - "G:/Xilinx/generator_kombinacji/generator_komb.vhd" line 56: The following signals are missing in the process sensitivity list: sekunda, czekaj. WARNING:Xst:819 - "G:/Xilinx/generator_kombinacji/generator_komb.vhd" line 81: The following signals are missing in the process sensitivity list: sekunda, reset. INFO:Xst:1304 - Contents of register <MAX> in unit <generator_komb> never changes during circuit operation. The register is replaced by logic. Entity <generator_komb> analyzed. Unit <generator_komb> generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit <generator_komb>. Related source file is "G:/Xilinx/generator_kombinacji/generator_komb.vhd". WARNING:Xst:646 - Signal <i> is assigned but never used. WARNING:Xst:646 - Signal <A_temp<3>> is assigned but never used. WARNING:Xst:646 - Signal <ind_temp> is assigned but never used. WARNING:Xst:646 - Signal <LED_temp> is assigned but never used. WARNING:Xst:646 - Signal <il_komb> is assigned but never used. WARNING:Xst:737 - Found 32-bit latch for signal <K<22>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<17>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<7>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<13>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<49>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<22>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<17>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<7>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<13>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<49>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<3>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<7>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<50>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<45>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<13>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<49>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<3>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<50>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<45>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<3>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<41>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<36>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<50>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<45>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<41>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<36>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<32>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<27>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<41>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<36>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<32>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<27>_2>. WARNING:Xst:737 - Found 1-bit latch for signal <sekunda>. WARNING:Xst:737 - Found 32-bit latch for signal <K<23>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<18>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<32>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<27>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<23>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<18>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<8>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<14>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<23>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<18>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<8>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<14>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<4>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<8>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<10>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<46>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<14>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<4>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<10>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<46>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<4>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<42>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<37>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<10>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<46>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <A_temp_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<42>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<37>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <A_temp_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<33>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<28>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<42>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<37>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<33>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<28>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <A_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<24>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<19>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<33>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<28>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <A_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<24>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<19>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<9>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<20>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<15>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <A_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<24>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<19>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<9>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<20>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<15>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<5>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<9>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<11>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<47>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<20>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<15>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<5>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<11>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<47>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<1>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<5>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <s>. WARNING:Xst:737 - Found 32-bit latch for signal <K<43>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<38>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<11>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<47>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<1>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <w>. WARNING:Xst:737 - Found 32-bit latch for signal <z>. WARNING:Xst:737 - Found 32-bit latch for signal <K<43>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<38>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<1>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<34>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<29>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<43>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<38>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<34>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<29>_2>. WARNING:Xst:737 - Found 1-bit latch for signal <reset>. WARNING:Xst:737 - Found 32-bit latch for signal <K<30>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<25>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<34>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<29>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<30>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<25>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<21>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<16>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<30>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<25>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<21>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<16>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<6>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<12>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<48>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<21>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<16>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<6>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<12>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<48>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<2>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<6>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<44>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<39>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<12>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<48>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<2>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<44>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<39>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<2>_3>. WARNING:Xst:737 - Found 1-bit latch for signal <start_zegar>. WARNING:Xst:737 - Found 32-bit latch for signal <K<40>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<35>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<44>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<39>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <ilosc_komb>. WARNING:Xst:737 - Found 32-bit latch for signal <K<40>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<35>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<31>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<26>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<40>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<35>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<31>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <K<26>_2>. WARNING:Xst:737 - Found 32-bit latch for signal <ind>. WARNING:Xst:737 - Found 7-bit latch for signal <LED>. WARNING:Xst:737 - Found 32-bit latch for signal <K<22>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<17>_1>. WARNING:Xst:737 - Found 32-bit latch for signal <K<31>_3>. WARNING:Xst:737 - Found 32-bit latch for signal <K<26>_3>. Found 4x1-bit ROM for signal <$mux0227> created at line 63. Found 4x1-bit ROM for signal <$mux0308> created at line 63. Found 16x7-bit ROM for signal <$mux0363>. WARNING:Xst:737 - Found 1-bit latch for signal <EOC>. INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. WARNING:Xst:737 - Found 3-bit latch for signal <next_state>. INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. Found 32-bit adder for signal <$addsub0000>. Found 32-bit adder for signal <$addsub0001> created at line 171. Found 32-bit adder for signal <$addsub0002> created at line 169. Found 32-bit adder for signal <$addsub0003> created at line 125. Found 32-bit subtractor for signal <$addsub0004> created at line 131. Found 32-bit adder for signal <$addsub0005> created at line 123. Found 32-bit adder for signal <$addsub0006> created at line 123. Found 32-bit adder for signal <$addsub0007> created at line 123. Found 32-bit comparator greater for signal <$cmp_gt0000> created at line 107. Found 32-bit comparator lessequal for signal <$cmp_le0000> created at line 139. Found 32-bit comparator lessequal for signal <$cmp_le0001> created at line 140. Found 32-bit comparator greater for signal <$cmp_lt0000> created at line 109. Found 32-bit comparator greater for signal <$cmp_lt0001> created at line 109. Found 32-bit comparator less for signal <$cmp_lt0002> created at line 127. Found 32-bit 4-to-1 multiplexer for signal <$mux0359> created at line 87. Found 1-bit 64-to-1 multiplexer for signal <$mux0364> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0365> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0366> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0367> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0368> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0369> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0370> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0371> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0372> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0373> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0374> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0375> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0376> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0377> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0378> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0379> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0380> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0381> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0382> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0383> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0384> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0385> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0386> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0387> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0388> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0389> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0390> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0391> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0392> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0393> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0394> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0395> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0396> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0397> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0398> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0399> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0400> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0401> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0402> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0403> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0404> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0405> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0406> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0407> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0408> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0409> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0410> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0411> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0412> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0413> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0414> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0415> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0416> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0417> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0418> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0419> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0420> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0421> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0422> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0423> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0424> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0425> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0426> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0427> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0428> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0429> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0430> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0431> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0432> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0433> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0434> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0435> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0436> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0437> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0438> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0439> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0440> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0441> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0442> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0443> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0444> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0445> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0446> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0447> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0448> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0449> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0450> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0451> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0452> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0453> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0454> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0455> created at line 150. Found 1-bit 64-to-1 multiplexer for signal <$mux0456> created at line 150. Found 32-bit subtractor for signal <$sub0003> created at line 123. Found 32-bit subtractor for signal <$sub0004> created at line 123. Found 32-bit subtractor for signal <$sub0005> created at line 123. Found 32-bit up counter for signal <czekaj>. Summary: inferred 3 ROM(s). inferred 1 Counter(s). inferred 11 Adder/Subtractor(s). inferred 6 Comparator(s). Unit <generator_komb> synthesized. INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. ========================================================================= HDL Synthesis Report Macro Statistics # ROMs : 3 16x7-bit ROM : 1 4x1-bit ROM : 2 # Adders/Subtractors : 11 32-bit adder : 7 32-bit subtractor : 4 # Counters : 1 32-bit up counter : 1 # Latches : 166 1-bit latch : 4 3-bit latch : 1 32-bit latch : 160 7-bit latch : 1 # Comparators : 6 32-bit comparator greater : 3 32-bit comparator less : 1 32-bit comparator lessequal : 2 # Multiplexers : 94 1-bit 64-to-1 multiplexer : 93 32-bit 4-to-1 multiplexer : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Macro Statistics # ROMs : 3 16x7-bit ROM : 1 4x1-bit ROM : 2 # Adders/Subtractors : 11 32-bit adder : 7 32-bit subtractor : 4 # Counters : 1 32-bit up counter : 1 # Registers : 32 Flip-Flops : 32 # Latches : 166 1-bit latch : 4 3-bit latch : 1 32-bit latch : 160 7-bit latch : 1 # Multiplexers : 94 1-bit 64-to-1 multiplexer : 93 32-bit 4-to-1 multiplexer : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit <generator_komb> ... implementation constraint: INIT=r : czekaj_31 implementation constraint: INIT=r : czekaj_7 implementation constraint: INIT=r : czekaj_21 implementation constraint: INIT=r : czekaj_30 implementation constraint: INIT=r : czekaj_29 implementation constraint: INIT=r : czekaj_28 implementation constraint: INIT=r : czekaj_27 implementation constraint: INIT=r : czekaj_26 implementation constraint: INIT=r : czekaj_25 implementation constraint: INIT=r : czekaj_24 implementation constraint: INIT=r : czekaj_23 implementation constraint: INIT=r : czekaj_22 implementation constraint: INIT=r : czekaj_20 implementation constraint: INIT=r : czekaj_19 implementation constraint: INIT=r : czekaj_18 implementation constraint: INIT=r : czekaj_17 implementation constraint: INIT=r : czekaj_16 implementation constraint: INIT=r : czekaj_15 implementation constraint: INIT=r : czekaj_14 implementation constraint: INIT=r : czekaj_13 implementation constraint: INIT=r : czekaj_12 implementation constraint: INIT=r : czekaj_11 implementation constraint: INIT=r : czekaj_10 implementation constraint: INIT=r : czekaj_9 implementation constraint: INIT=r : czekaj_8 implementation constraint: INIT=r : czekaj_6 implementation constraint: INIT=r : czekaj_5 implementation constraint: INIT=r : czekaj_4 implementation constraint: INIT=r : czekaj_3 implementation constraint: INIT=r : czekaj_2 implementation constraint: INIT=r : czekaj_1 implementation constraint: INIT=r : czekaj_0 ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- WARNING:ProjectMgmt - "G:/Xilinx/generator_kombinacji/generator_komb.ngr" line 0 duplicate design unit: 'Module|generator_komb'

I niby rpzechodzi to synthetize XST bo zielona fajka jest, ale jest też wykrzyknik! To to będzie działąć jak jutro pójde do doktora sprawdzić na płytce???? mimo tego wykrzyknika?

Mój program jest taki:

Kod: Zaznacz cały

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity generator_komb is generic( n_calk: integer :=6; --max 15,jesli chce sie wiecej trzeba odpowiednio zwiekszyc zakres nowo zdefiniowanych w programie typow danych k_calk: integer :=3 ); port(CLK: in std_logic; START: in bit; EOC: out bit; LED: out STD_LOGIC_VECTOR (6 downto 0) ); end generator_komb; architecture Behavioral of generator_komb is type tablica is array (1 to 50, 1 to k_calk) of integer; type tablica2 is array (1 to k_calk) of integer; signal present_state, next_state: integer range 1 to 7; signal A: tablica2; signal K: tablica; signal ind: integer; signal czekaj: integer :=0; signal reset: bit :='0'; signal sekunda: bit; signal start_zegar: bit :='0'; begin zegar: process(start_zegar, clk, reset) is begin if(start_zegar='1')then if(reset='0')then sekunda <= '0'; reset <= start_zegar; end if; if(sekunda='0')then if((clk'event)and(clk='1'))then czekaj <= czekaj + 1; end if; if(czekaj=100000)then sekunda <= '1'; czekaj <= 0; reset <= '0'; end if; end if; end if; end process zegar; takt: process (next_state) is begin present_state <= next_state; end process takt; main: process(start, present_state) variable i, MAX, s, ind_temp, w, z, il_komb, ilosc_komb: integer; variable A_temp: tablica2; variable LED_temp: STD_LOGIC_VECTOR (6 downto 0); begin if(start = '1')then case present_state is when 1 => ind <= 1; --ind=1 MAX := n_calk-k_calk+1; --MAX=n-k+1 s := 1; --s=1 next_state <= 2; when 2 => for i in 1 to k_calk loop--ONE2SUBSET A_temp(i) := s; end loop; A <= A_temp; s := A_temp(ind)+1; --s=2 next_state <= 3; when 3 => for i in 1 to k_calk loop --OUTPUT K(1,i) <= A(i)+i-1; --mamy 1 kombinację umieszczoną w tablicy end loop; ind <= k_calk; --ind=k ilosc_komb:=1; -- liczymy sobie ile mamy kombinacji by moc potem wyprowadzic dane na wyswietlacz next_state <= 4; when 4 => if(ind>0)then --while(ind>0)do F0: for i in k_calk downto 1 loop --ONE2SUBSET A_temp(i) := s; exit F0 when (i<ind); end loop F0; A <= A_temp; next_state <= 5; else --while(!ind>0)do EOC <= '1'; --EOC=1 - dioda informujaca, ze koniec generowania kombinacji start_zegar <= '1'; --start_zegar=1 oznacza, ze kolejne kombinacje za 1 sekunde zaczna pojawiac sie na wyswietlaczu w := 1; --ustawienie pozycji wiersza macierzy K (zawierajacej kombinacje) na 1 z := 1; --ustawienie pozycji kolumny macierzy K na 1 next_state <= 6; end if; when 5 => for i in 1 to k_calk loop --OUTPUT K(1+ilosc_komb,i) <= A(i)+i-1; end loop; il_komb := ilosc_komb+1; --liczymy sobie ilosc kombinacji dotychczas wygenerowanych ilosc_komb := il_komb; if(A(ind)<MAX) then s := A(ind)+1; ind <= k_calk; else ind_temp := ind-1; ind <= ind_temp; s := A(ind_temp)+1; end if; next_state <= 4; when 6 => if(sekunda='1')then start_zegar <= reset; -- zablokowanie odliczania 1 sekundy (start_zegar=0) if(w<=ilosc_komb) then if(z<=k_calk) then -- podlaczenie segmentow wyswietlacza -- do kolejnych bitow zmiennej LED -- 0 -- --- -- 5 | | 1 -- --- <- 6 -- 4 | | 2 -- --- -- 3 case K(w,z) is when 1 => LED_temp:="1111001"; --1 when 2 => LED_temp:="0100100"; --2 when 3 => LED_temp:="0110000"; --3 when 4 => LED_temp:="0011001"; --4 when 5 => LED_temp:="0010010"; --5 when 6 => LED_temp:="0000010"; --6 when 7 => LED_temp:="1111000"; --7 when 8 => LED_temp:="0000000"; --8 when 9 => LED_temp:="0010000"; --9 when 10 => LED_temp:="0001000"; --A when 11 => LED_temp:="0000011"; --b when 12 => LED_temp:="1000110"; --C when 13 => LED_temp:="0100001"; --d when 14 => LED_temp:="0000110"; --E when 15 => LED_temp:="0001110"; --F when others => LED_temp:="1000000" ;--0 end case; LED <= LED_temp; z := z+1; else w := w+1; z := 1; LED <= "1011111"; --- pomiedzy kolejnymi kombinacjami na wyswietlaczu pojawia sie kreska pozioma end if; end if; next_state <= 7; end if; when 7 => start_zegar <= '1'; next_state <=6; end case; else -- jesli start=0; next_state <= 1; EOC <= '0'; end if; end process main; end Behavioral;



Ten program jest generatorem kombinacji 3 z 6 bez powtórzeń, który w pseudokodzie wygląda tak:

Kod: Zaznacz cały

MAX=n-k+1; ind=1; s=1; //poniższa instrukcja for ma być wykonana równolegle for(i=ind;i<=k;i++) A(i)=s; //koniec wykonywania równolegle s=A(ind)+1; //ponownie wykonuj równolegle instrukcje for for(i=1;i<=k;i++) K(i)=A(i)+i-1; // koniec równoległości z tym, że również ma być tu druga równoległość a mianowicie razem z równoległym przypisywaniem w for ma się wykonać poniższa instrukcja: ind=k; //koniec równoległości while ind>0 do { //poniższa instrukcja for ma być wykonana równolegle for(i=ind;i<=k;i++) A(i)=s; //koniec wykonywania równolegle //ponownie wykonuj równolegle instrukcje for for(i=1;i<=k;i++) K(i)=A(i)+i-1; // koniec równoległości z tym, że również ma być tu druga równoległość a mianowicie razem z równoległym przypisywaniem w for ma się wykonać poniższa instrukcja: if A(ind)<MAX then s=A(ind)+1; ind=k; else ind=ind-1; s = A(ind)+1 //koniec równoległości }
W wyniku tego algorytmu takie coś mamy np. dla kombinacji n=6 k=3 (bez powtórzeń):
ind s A K
1 1 111 123
3 2 112 124
3 3 113 125
3 4 114 126
2 2 122 134
itd.
czyli K zawiera tą tablice właściwą z kombinacjami.

anderson20
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Postautor: anderson20 » 5 lut 2009, o 09:42

Problem rozwiązany. Otóż uczelnia dysponuje tylko układem CPDL o pojemności 256 makrokomórek (tj. Cool Runner II XC2C256-7TQ144) no i za pomocą takiego układu nie da się napisać tego programu, bo ilość makrokomórek wymaganych jest kilka razy większa a już bardziej kodu zoptymalizować się nie da.

Piotr Czak
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Postautor: Piotr Czak » 5 lut 2009, o 12:10

Cześć,

no niby tak problem rozwiązany, ponieważ prowadzący nie czepiał się bardzo. Gdyby się czepiał.

To co moge napisać ja:
1. Kod ewidentnie nie został przez Ciebie przesymulowany na symulatorze ponieważ info ktore sie pojawilo:
INFO:Xst:1433 - Contents of array <A> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
właśnie o tym mi mówi, no i jednocześnie ja to przesymulowałem. W stanie 4masz:

Kod: Zaznacz cały

when 4 => if(ind>0)then --while(ind>0)do F0: for i in k_calk downto 1 loop --ONE2SUBSET A_temp(i) := s; exit F0 when (i<ind); end loop F0; A <= A_temp; next_state <= 5; else --while(!ind>0)do EOC <= '1'; --EOC=1 - dioda informujaca, ze koniec generowania kombinacji start_zegar <= '1'; --start_zegar=1 oznacza, ze kolejne kombinacje za 1 sekunde zaczna pojawiac sie na wyswietlaczu w := 1; --ustawienie pozycji wiersza macierzy K (zawierajacej kombinacje) na 1 z := 1; --ustawienie pozycji kolumny macierzy K na 1 next_state <= 6; end if; when 5 => for i in 1 to k_calk loop --OUTPUT K(1+ilosc_komb,i) <= A(i)+i-1; end loop; il_komb := ilosc_komb+1; --liczymy sobie ilosc kombinacji dotychczas wygenerowanych ilosc_komb := il_komb; if(A(ind)<MAX) then s := A(ind)+1; ind <= k_calk; else ind_temp := ind-1; ind <= ind_temp; s := A(ind_temp)+1; end if; next_state <= 4; zakładamy ze ind = 1 wiec idziemy do stanu 5 w którym to masz: ind_temp := ind-1; --ind_temp jest rowne 0 ind <= ind_temp; --ind jest rowne 0 s := A(ind_temp)+1; --A(0) nie isteniej BLAD
Kolejna sprawa projekt da sie jeszcze zoptymalizować tak by miał szanse zmieścic się na danym układzie FPGA, teraz nie mam za wiele czasu by to zrobić, postaram się po weekendzie, który dla mnie zaczyna sie dzisiaj :)

petle for w vhdl to nie jest to samo co petle for w c++
rownoleglosci mozna rozwiazac inaczej poniewaz jest to znaczenie wzgledne, czyli wzgledem czego cos ma byc rownolegle itp.

Pozdrawiam

Edit: Zauważyłem, że nigdzie nie używasz znacznika

Kod: Zaznacz cały

, może jednak warto się przełamać, to się naprawdę znacznie lepiej czyta. Pajączek. [/color]
Ostatnio zmieniony 5 lut 2009, o 13:40 przez Piotr Czak, łącznie zmieniany 1 raz.

Piotr Czak
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Postautor: Piotr Czak » 5 lut 2009, o 15:10

Witam,

moja propozycja tego kodu:

Kod: Zaznacz cały

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity generator_komb is generic( n_calk : integer :=6; --max 15,jesli chce sie wiecej trzeba odpowiednio zwiekszyc zakres nowo zdefiniowanych w programie typow danych k_calk : integer :=3 ); port( CLK : in std_logic; RST : in std_logic; START : in bit; EOC : out bit; LED : out STD_LOGIC_VECTOR (6 downto 0) ); end generator_komb; architecture Behavioral of generator_komb is type tablica is array (1 to 50, 1 to k_calk) of integer range 0 to 15; type tablica2 is array (1 to k_calk) of integer; signal present_state : integer range 1 to 8; signal next_state : integer range 1 to 8; signal A : tablica2; signal K : tablica; signal ind : integer; signal czekaj : integer range 0 to 131071 :=0; signal reset : bit :='0'; signal sekunda : bit; signal start_zegar : bit :='0'; begin zegar: process(RST, CLK) is begin if (RST = '1') then sekunda <= '0'; czekaj <= 0; elsif (rising_edge(CLK)) then if(czekaj = 100000)then sekunda <= '1'; czekaj <= 0; else czekaj <= czekaj + 1; sekunda <= '0'; end if; end if; end process zegar; takt: process (next_state) is begin present_state <= next_state; end process takt; main: process(RST, CLK) variable i, MAX, s, ind_temp, w, z, il_komb, ilosc_komb: integer; variable counter_0 : integer range 0 to k_calk + 1; variable A_temp: tablica2; variable LED_temp: STD_LOGIC_VECTOR (6 downto 0); begin if (RST = '1') then next_state <= 1; counter_0 := 1; elsif (rising_edge(CLK)) then if (start = '1') then case present_state is when 1 => ind <= 1; --ind=1 MAX := n_calk-k_calk+1; --MAX=n-k+1 s := 1; --s=1 counter_0 := 1; next_state <= 2; when 2 => if (counter_0 > k_calk) then A <= A_temp; s := A_temp(ind)+1; --s=2 counter_0 := 1; next_state <= 3; else A_temp(counter_0) := s; counter_0 := counter_0 + 1; next_state <= 2; end if; when 3 => if (counter_0 > k_calk) then ind <= k_calk; --ind=k ilosc_komb :=1; -- liczymy sobie ile mamy kombinacji by moc potem wyprowadzic dane na wyswietlacz next_state <= 4; counter_0 := k_calk; else K(1,counter_0) <= A(counter_0)+counter_0-1; --mamy 1 kombinacj? umieszczon? w tablicy counter_0 := counter_0 + 1; next_state <= 3; end if; when 4 => if(ind > 1)then --while(ind>0)do if ((counter_0 < 1) or (counter_0 < ind)) then A <= A_temp; next_state <= 5; counter_0 := 1; else A_temp(counter_0) := s; counter_0 := counter_0 - 1; next_state <= 4; end if; else --while(!ind>0)do EOC <= '1'; --EOC=1 - dioda informujaca, ze koniec generowania kombinacji start_zegar <= '1'; --start_zegar=1 oznacza, ze kolejne kombinacje za 1 sekunde zaczna pojawiac sie na wyswietlaczu w := 1; --ustawienie pozycji wiersza macierzy K (zawierajacej kombinacje) na 1 z := 1; --ustawienie pozycji kolumny macierzy K na 1 next_state <= 6; end if; when 5 => if (counter_0 > k_calk) then il_komb := ilosc_komb+1; --liczymy sobie ilosc kombinacji dotychczas wygenerowanych ilosc_komb := il_komb; if(A(ind) < MAX) then s := A(ind)+1; ind <= k_calk; else ind_temp := ind-1; ind <= ind_temp; s := A(ind_temp)+1; end if; counter_0 := k_calk; next_state <= 4; else K(1+ilosc_komb,counter_0) <= A(counter_0)+counter_0-1; counter_0 := counter_0 + 1; next_state <= 5; end if; when 6 => if(sekunda='0')then next_state <= 7; else next_state <= 6; end if; when 7 => if(sekunda='1')then start_zegar <= reset; -- zablokowanie odliczania 1 sekundy (start_zegar=0) if(w<=ilosc_komb) then if(z<=k_calk) then -- podlaczenie segmentow wyswietlacza -- do kolejnych bitow zmiennej LED -- 0 -- --- -- 5 | | 1 -- --- <- 6 -- 4 | | 2 -- --- -- 3 case K(w,z) is when 1 => LED_temp:="1111001"; --1 when 2 => LED_temp:="0100100"; --2 when 3 => LED_temp:="0110000"; --3 when 4 => LED_temp:="0011001"; --4 when 5 => LED_temp:="0010010"; --5 when 6 => LED_temp:="0000010"; --6 when 7 => LED_temp:="1111000"; --7 when 8 => LED_temp:="0000000"; --8 when 9 => LED_temp:="0010000"; --9 when 10 => LED_temp:="0001000"; --A when 11 => LED_temp:="0000011"; --b when 12 => LED_temp:="1000110"; --C when 13 => LED_temp:="0100001"; --d when 14 => LED_temp:="0000110"; --E when 15 => LED_temp:="0001110"; --F when others => LED_temp:="1000000" ;--0 end case; LED <= LED_temp; z := z+1; else w := w+1; z := 1; LED <= "1011111"; --- pomiedzy kolejnymi kombinacjami na wyswietlaczu pojawia sie kreska pozioma end if; end if; next_state <= 8; end if; when 8 => start_zegar <= '1'; next_state <=6; end case; else next_state <= 1; EOC <= '0'; end if; end if; end process main; end Behavioral;
teraz dalem

Kod: Zaznacz cały

zapomnialem o tym, dziekuje ze przypomnienie. ten kod nie zawiera for'ow wiec powinno sie to dac zsyntezowac i zimplementowac na uklad. Warto jeszcze ograniczyc sobie zakresy dla integerow. No i prosze o sprawdzenie czy wyswietlane warosci sa prawidlowe. Jak będzie trzeba moge również przesłać kod testbencha ale wydaje mi sie ze autor nie bedzie mial z tym problemu. Pozdrawiam

anderson20
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Postautor: anderson20 » 6 lut 2009, o 13:39

Niestety nie przeszedł projekt, bo gość chce by na 4 wyświetlaczach to chulało jak k=4, na 3 wyświetlaczach jak k=3 itp aby jednocześnie wyświetlało kombinację i nie chce by pamiętać wszystkich kombinacji, tylko aktualną sekwencję dzięki czemu nie przekroczy się dostępnej pamięci na płytce. I zmodyfikowałem kod odpowiednio i przeszedł wszystkie checksyntaxy itd.

Kod: Zaznacz cały

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity generator_komb is generic( n_calk: integer :=6; k_calk: integer :=3 ); port(CLK: in std_logic; START: in std_logic; EOC: out std_logic :='0'; LED: out STD_LOGIC_VECTOR (6 downto 0); wys_led: out STD_LOGIC_VECTOR(3 downto 0) ); end generator_komb; architecture Behavioral of generator_komb is type tablica is array (1 to 15) of integer range 0 to 15; signal present_state, next_state: integer range 0 to 5; signal A, K: tablica; signal ind, s, MAX: integer range 1 to 15; signal nr_led: std_logic_vector (1 downto 0) :="00"; signal wysw: integer range 0 to 15; signal czekaj: std_logic_vector(19 downto 0) :=X"00000"; signal sekunda: bit :='0'; begin zegar: process(clk) is begin if((clk'event)and(clk='1'))then --jesli narastajace zbocze zegara if(nr_led="11")then --jesli nr_led="11" nr_led <= "00"; --to wyzeruj nr_led else --w przeciwnym wypadku nr_led <= nr_led + "01"; --zwiększ nr_led o 1; end if; if(czekaj=X"186A0")then --jesli sygnał czekaj=100000d sekunda <= not sekunda; --zaneguj bit sekunda na przeciwny czekaj <= X"00000"; --wyzeruj sygnał czekaj else --jesli sygnał czekaj /= 100000d czekaj <= czekaj + X"00001"; --zwieksz sygnal czekaj o 1d end if; end if; end process zegar; takt: process (next_state, sekunda) is begin if(sekunda='1')then present_state <= next_state; end if; end process takt; main: process(start, present_state) variable i, ind_temp: integer range 1 to 15; variable A_temp: tablica; begin if(start = '1')then case present_state is when 1 => ind <= 1; --ind=1 MAX <= n_calk-k_calk+1; --MAX=n-k+1 s <= 1; --s=1 next_state <= 2; when 2 => for i in 1 to k_calk loop--ONE2SUBSET A_temp(i) := s; end loop; A <= A_temp; s <= A_temp(ind)+1; --s=2 next_state <= 3; when 3 => for i in 1 to k_calk loop --OUTPUT K(i) <= A(i)+i-1; --mamy 1 kombinację umieszczoną w tablicy end loop; ind <= k_calk; --ind=k next_state <= 4; when 4 => if(ind>0)then --while(ind>0)do F0: for i in k_calk downto 1 loop --ONE2SUBSET A_temp(i) := s; exit F0 when (i<ind); end loop F0; A <= A_temp; next_state <= 5; else --while(!ind>0)do EOC <= '1'; --EOC=1 - dioda informujaca, ze koniec generowania kombinacji end if; when 5 => for i in 1 to k_calk loop --OUTPUT K(i) <= A(i)+i-1; end loop; if(A(ind)<MAX) then s <= A(ind)+1; ind <= k_calk; else ind_temp := ind-1; ind <= ind_temp; if(ind_temp/=0)then s <= A(ind_temp)+1; end if; end if; next_state <= 4; when others => next_state <= 1; --kiedy nacisniemy przycisk startu automat stanu zaczyna swoją pracę end case; else -- jesli start=0; next_state <= 0; --zresetuj automat stanu EOC <= '0'; for i in 1 to 15 loop K(i) <= 0; end loop; end if; end process main; --wybor wyswietlacz with nr_led select wys_led <= "1110" when "00", "1101" when "01", "1011" when "10", "0111" when "11", "1111" when others; --wybor pozycji wektora K to wyswietlenia with nr_led select wysw <= K(1) when "00", K(2) when "01", K(3) when "10", K(4) when "11", 0 when others; --konwerter kodu with wysw Select LED <= "1111001" when 1, --1 "0100100" when 2, --2 "0110000" when 3, --3 "0011001" when 4, --4 "0010010" when 5, --5 "0000010" when 6, --6 "1111000" when 7, --7 "0000000" when 8, --8 "0010000" when 9, --9 "0001000" when 10, --A "0000011" when 11, --b "1000110" when 12, --C "0100001" when 13, --d "0000110" when 14, --E "0001110" when 15, --F "1111111" when others; --nic end Behavioral;
I może bedzie działać, ale jeszcze gość chce by mu testbencha zrobić a tego to za chuja nie umię, bo jak utworze text bench waveform i potem daję na Simulate Behavioral Model to wypierdala takie błędy:
Running Fuse ...
WARNING:HDLParsers:3215 - Unit work/test is now defined in a different file: was G:/Xilinx/generator_kombinacji/test.ant, now is G:/Xilinx/generator_kombinacji/test.vhw
WARNING:HDLParsers:3215 - Unit work/test/testbench_arch is now defined in a different file: was G:/Xilinx/generator_kombinacji/test.ant, now is G:/Xilinx/generator_kombinacji/test.vhw
Compiling vhdl file "G:/Xilinx/generator_kombinacji/test.vhw" in Library work.
Entity <test> compiled.
Entity <test> (Architecture <testbench_arch>) compiled.
Parsing "test_beh.prj": 0.05
Codegen work/test: 0.00
ERROR:Simulator:418 - Compilation failed: g++.exe: Nie moÂ&iquest;na odnale &Atilde;&brvbar; okre lonego pliku..
ERROR:Simulator:222 - Generated C++ compilation was unsuccessful
Codegen work/test/testbench_arch: 0.02

Piotr Czak
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Postautor: Piotr Czak » 8 lut 2009, o 18:19

Witam,

TestBencha pisze się bardzo prosto, o to taki jak potrzebujesz:

Kod: Zaznacz cały

entity TestBench is generic( n_calk : integer :=6; k_calk : integer :=3 ); end TestBench; architecture Behavioral of TestBench is component generator_komb is generic( n_calk : integer :=6; k_calk : integer :=3 ); port( CLK : in std_logic; START : in std_logic; EOC : out std_logic :='0'; LED : out STD_LOGIC_VECTOR (6 downto 0); wys_led : out STD_LOGIC_VECTOR(3 downto 0) ); end component; signal CLK : std_logic; signal START : std_logic; signal EOC : std_logic :='0'; signal LED : STD_LOGIC_VECTOR (6 downto 0); signal wys_led : STD_LOGIC_VECTOR(3 downto 0); begin U0 : generator_komb generic map( n_calk => n_calk, k_calk => k_calk ) port map( CLK => CLK, START => START, EOC => EOC, LED => LED, wys_led => wys_led ); clock: process is begin CLK <= '0'; wait for 20ns; CLK <= '1'; wait for 20ns; end process; stimulus: process is begin START <= '0'; wait for 200ns; START <= '1'; wait; end process; end Behavioral;
Teraz jak sobie przesymulujesz wyjdzie Ci, że masz wprojekcie błąd. Napewno pojawiło Ci sie coś takiego:

Kod: Zaznacz cały

INFO:Xst:1433 - Contents of array <A> may be accessed with an index that exceeds the array size. This could cause simulation mismatch. INFO:Xst:1432 - Contents of array <A> may be accessed with a negative index, causing simulation mismatch. INFO:Xst:1433 - Contents of array <A> may be accessed with an index that exceeds the array size. This could cause simulation mismatch.
Dodatkowa sprawa podczas symulacji i tak Ci wyjdzie jeszcze kilka innych rzeczy w Twoim projekcie.

Ciekawi mnie również, czy po tych zmianach które wprowadziłeś zmieści Ci się to na układzie i ile to się będzie syntezować. W późniejszym czasie polecam zapoznać się z moją propozycją realizacji tego projektu.

Pozdrawiam

anderson20
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Postautor: anderson20 » 9 lut 2009, o 10:30

Tzn. przed ostatnimi zmianami czyli w środę nie chciało się zsymulować, bo tam nie dawałem zakresu dla sygnałów, zmiennych typu integer i miałem tablicę 2-wymiarową K, bo chciałem pamiętać wszystkie wygenerowane kombinacje oraz był ten błąd z tą tablicą A co przekracza granicę indeksowania a na który to błąd mi wskazałeś. Teraz już nie ma tych błędów, bo nie musi być tablica 2-wymiarowa (tylko trzeba pamiętać aktualnie co jest na wyjściu) i wyeliminowałem błąd z A jak i dałem zakresy dla integerów czy zmieniłem je na typy bitowe. Twój kod wiem, że działa tylko nie przeszedłby u mojego prowadzącego niestety bo prowadzący chce by równolegle następowało przypisywanie np. do tablicy A,K czy tam inne równoległości by były zachowane. Czyli testbencha dosyć ciężko się robi jak widzę, ale dzisiaj oddaję i może przejdzie bez testbencha najwyżej 3 bedzie i grunt, że zaliczone.

Piotr Czak
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Posty:22
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Postautor: Piotr Czak » 9 lut 2009, o 13:04

Witam

TestBench pisze się bardzo łatwo, załączyłem w poprzedniej odpowiedzi taki jaki jest Ci potrzebny. Co do równoległości szeregowości i innych dziwnych wyrazów to tak jak napisałem są to pojęcia względne. Chodzi o to, by cała tablica była zapisana przed kolejną operacją, co jest zrobione, ma sie wyrabiac w czasie jest zrobione.

Osobiście nie widze problemów. No ale to nie moja sprawa jak prowadzacy tak chce to niech ma.

Pozdrawiam

PS. Co za uczelnia?

Wróć do „PLD/FPGA i inne zagadnienia techniki cyfrowej”

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